This invention relates to semiconductor memory devices, and more particularly to MOS read-only type memories of the virtual ground type.
Floating gate type electrically programmable ROM devices have been thus far manufactured using cell layouts as seen in U.S. Pat. Nos. 4,112,509 and 4,112,544, issued to Wall and McElroy, assigned to Texas Instruments. Several manufacturers produce EPROM devices of these or similar layouts in 8K, 16K, 32K and recently 64K bit sizes. The continuing demand for higher speed and lower cost, however, requires reduction in cell size or increase in bit density. One of the classic techniques for increasing the array density in read-only type memories (ROMs or EPROMs) is to use virtual grounds instead of providing a ground line for each column or output line. Virtual ground ROMs are disclosed in U.S. Pat. No. 3,934,233 issued to Fisher and Rogers or U.S. Pat. No. 4,021,781 issued to E. R. Caudel, both assigned to Texas instruments. The currents and high voltages required in programming of floating gate EPROMs place more stringent demands on the decode circuitry previously employed in virtual ground devices. This is the reason that prior EPROM layouts used separate contacts and lines to each cell, which unfortunately uses excess space on the chip.
It is the principal object of this invention to provide an improved EPROM or ROM device, which is of smaller size or greater bit density. Another object is to provide improved decode circuitry for "virtual ground" type memory devices. A further object is to provide an arrangement for accessing a memory array for read and/or programming in an improved manner.